ADI：ADSP-SC598 SHARC+ Dual-Core DSP介绍及应用

简介
Analog Devices ADSP-SC598 处理器执行实时处理任务并管理用于接口音频应用中关键时间数据的外围设备

模拟器件ADSP-SC598处理器是SH RC®系列产品的成员。它们包含SH RC+®双核和Arm® Cortex®-A55核心，使它们能够处理额外的实时处理任务，并管理用于接口音频应用中关键数据的外围设备。这些接口包括千兆以太网，USB高速，CAN FD和丰富的其他连接选项，以灵活和简化的系统设计。ADSP-SC598 处理器采用模拟器件超级哈佛架构。这些32位/40位/64位浮点处理器针对高性能音频/浮点应用进行了优化，采用大容量片内静态随机访问存储器（SRAM）、消除输入/输出（I/O）瓶颈的多个内部总线以及创新的数字音频接口（DAI）。SHARC+核心的新增功能包括增强缓存和分支预测同时保持指令集与以前SHARC产品的兼容性。

Analog Devices ADSP-SC598 processors perform real-time processing tasks and manage peripherals used to interface time-critical data in audio applications

Analog Devices ADSP-SC598 processors are members of the SHARC® family of products. They contain the SHARC+® dual-core and the Arm® Cortex®-A55 core, allowing them to handle additional real-time processing tasks and to manage peripherals used to interface time-critical data in audio applications. These interfaces include Gigabit Ethernet, USB high-speed, CAN FD, and a rich variety of other connectivity options for a flexible and simplified system design. ADSP-SC598 processors feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high-performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). Additions to the SHARC+ core include cache enhancements and branch prediction while maintaining instruction set compatibility to previous SHARC products.

特性

• Dual-enhanced SHARC+ high-performance floating-point cores

• 800 MHz (max) or 1 GHz (max) core clock frequency

• 5 Mb (640 kB) L1 SRAM memory per core with parity       (optional ability to configure as cache)

• 32-bit, 40-bit, and 64-bit floating point support

• 32-bit fixed point

• Byte, short-word, word, and long-word addressed

• Arm Cortex-A55 core

• Up to 1,200 MHz/3,360 DMIPS with advanced SIMD and       floating-point support

• 32 kB L1 instruction cache with parity and 32 kB L1       data cache with ECC

• 256 kB L2 cache with ECC

• Memory

• 2 MB on-chip L2 SRAM with ECC protection eliminates the       need for external memory

• One L3 interface optimized for low system power, providing       16-bit interface to DDR3/DDR3L devices

• Security and protection

• Cryptographic hardware accelerators

• Fast and secure boot with IP protection

• Supports Arm TrustZone and cryptographic extension

应用

汽车：音频放大器、头单元、ANC/RNC、后座娱乐、数字驾驶舱和ADAS

消费者和专业音频：扬声器、音响、AVR、会议系统、混音台、麦克风阵列和耳机

• Automotive: audio amplifiers, head units, ANC/RNC, rear seat      entertainment, digital cockpits, and ADAS

• Consumer and professional audio: speakers, sound bars, AVRs,      conferencing systems, mixing consoles, microphone arrays, and headphones

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